1. Field of the Invention
The present invention relates to semiconductor technology, and particularly relates to a semiconductor apparatus and a manufacturing method therefore. More specifically, the present invention relates to a semiconductor apparatus comprising an N-channel strained semiconductor device and manufacturing method therefore.
2. Description of the Related Art
With the development of semiconductor technology, the critical dimensions of a device have been continuously reduced. Stress memorization technology has been widely used as a strained device technology to enhance electrical performance of devices.
As known in the art, the amount of stress applied to a three-dimensional structure influences the performance of the final device. For example, an N-channel semiconductor device (such as, an NMOS field effect transistor, also referred to as an NMOS transistor), higher tensile stress can result in higher carrier mobility.
The prior art discloses a stress memorization technology (SMT) for an N-channel semiconductor device. As shown in FIG. 8, a dielectric layer 113 and a gate 101 are formed over a substrate 109. Preferably, a portion of the substrate 109 can include a lightly doped region (LDD) 105. A gate spacer 103 can then be formed along with implantations to form a source region 107 and a drain region 111. After the source region 107 and the drain region 111 implantations, stressing process is performed. The procedure for the stressing process according to the prior art can comprise depositing a stress material (such as silicon nitride) 801 above the substrate 109, performing an SMT etching to maintain the stress material over a N-channel semiconductor device region, annealing so that the stress is retained (i.e., forming strain); and removing the nitride stress material 801.
However, there still exists a need for a semiconductor apparatus comprising a semiconductor device having an enhanced strain and a manufacturing method therefore.